1 application note 1569 ISL28233MSOPEVAL2Z evaluation board user?s guide introduction the ISL28233MSOPEVAL2Z evaluation board is designed to evaluate the performance of the isl28233 chopper stabilized op amp. the evaluation board contains the circuitry needed to evaluate the high performance of the isl28233 amplifier. the isl28233 chopper stabilized rail-to-rail dual op amp features a low 8v maximum v os over-temperature and a 0.1hz 1/f noise corner frequency enabling very high gain single-s tage dc amplifiers that can operate from single cell batteries while consuming only 20a of current. the ISL28233MSOPEVAL2Z evaluation board can be configured as a precision high-gain (g = 10,000v/v) differential amplifier and demonstrates the level of performance possible with this type of amplifier while operating from battery voltages as low as 1.65v. reference documents ? isl28233 data sheet, fn7692 evaluation board key features ? single supply operation: +1.65v to +5.5v ? dual supply operation: 0.825v to 2.75v ? singled-ended or differential input operation with high gain (g = 10,000v/v) ?external vref input ? banana jack connectors for power supply and vref inputs ? bnc connectors for op amp input and output te r m i n a l s ? convenient pcb pads for op amp input/output impedance loading. power supplies (figure 2) external power connections are made through the v+, v-, vref, and gnd connections on the evaluation board. the circuit can operate from a single supply or from dual supplies. for single supply operation, the v- and gnd pins are tied together to the negative or ground reference of the power supply. for split supplies, v+ and v- terminals connect to their respective supply terminals. de-coupling capacitors c2 and c4 provide low-frequency power-supply filter ing, while additional capacitors, c3 and c5, which are connected close to the part, filter out high frequency noise. anti-reverse diode d1 (optional) protects the circuit in the momentary case of accidentally reversing the power supplies to the evaluation board. the vref pin can be connected to ground to establish a ground referenced input for split supply operation, or can be externally set to any reference level for single supply operation. figure 1. basic differential amplifier configuration vref in - in + gnd 1m open out isl28233 v- 0 vcm in- in+ vref v+ 100 100 - + 100k open r13/r23 r11/r24 r14/r21 r18/r19 r26/r27 1/7 r28/r29 ina- ina+ inb- inb+ 6 5 2 3 8 4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. october 5, 2010 an1569.1
2 an1569.1 october 5, 2010 amplifier configuration (figure 3) the schematic of the op amp input stage with the components supplied is shown in figure 3, with a closed loop gain of 10,000. the circuit implements a hi-z differential input with unbalanced common mode impedance. the differential amp lifier gain is expressed in equation 1: for single-ended input with an inverting gain g = -10,000v/v, the in+ input is grounded and the signal is supplied to the in- input. vref must be connected to a reference voltage between the v+ and v- supply rails. for non-inverting operation with g = 10,001v/v, the in- input is grounded and the signal is supplied to the in+ input. the non-inverting gain is strongly dependent on any resistance from in- to gnd. for good gain accuracy, a 0 resistor should be installed on the empty r5 pad. user-selectable options (figures 3 and 4) component pads are included to enable a variety of user-selectable circuits to be added to the amplifier inputs, the vref input, outputs and the amplifier feedback loops. a voltage divider (figure 3, r18 and r15) can be added to establish a power supply-tracking common mode reference using the vref input. the inverting and non-inverting inputs have additional resistor placements for adding input attenuation, or to establish input dc offsets through the vref pin. the output (figure 4) also has additional resistor and capacitor placements for filtering and loading. note: operational amplifiers are sensitive to output capacitance and may oscillate. in the event of oscillation, reduce output capacitance by using shorter cables, or add a resistor in series with the output. figure 2. power supply circuit r31 2 0 1f 0 1f j8 1 j6 1 2 3 j13 1 j12 1 j14 1 j11 1 3 c5 c4 c2 d1 1 2 3 r16 1 2 1 2 vref v+ v- 0.01f 0.01f c5 close to dut v out v in+ ( v in- ) r f ( ? r in ) ? ? v ref + = (eq. 1) in+a in-a dnp r5 r4 j2 j1 r1 r2 r14 r18 r15 r13 r11 100 dnp dnp 0 100 dnp 1m open 100k vref to ina - to ina + from outa figure 3. input stage c6 out a r26 j12 c8 r28 dnp open 0 figure 4. output stage c6 out_a table 1. ISL28233MSOPEVAL2Z components parts list device # description comments c2, c4 cap, smd, 1206, 1f, 50v, 10%, x7r, rohs power supply decoupling c3, c5 cap, smd, 0603, 0.1f, 50v, 10%, x7r, rohs power supply decoupling c1, c6, c7, c8, c9, c10 cap, smd, 0603, dnp-place holder, rohs user selectable capacitors - not populated r11, r14, r21, r24 resistor, smd, 0603, 100 , 1%, 1/16w, rohs gain setting resistor r13, r23 resistor, smd, 0603, 10m , 1%, 1/16w, rohs gain setting feedback resistor r1, r2, r3, r5, r6, r7, r8, r10, r12, r15, r17, r20, r22, r28, r29, r30, r32, r34, r35, r36 resistor, smd, 0603, dnp-place holder, rohs us er selectable resistors - not populated d1 40v series schottky barrier diode reverse power protection u1 (isl28233fuz) isl2 8233fuz, ic-rail-to-rail op amp, msop, rohs application note 1569
3 intersil corporation reserves the right to make changes in circui t design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1569.1 october 5, 2010 application note 1569 ISL28233MSOPEVAL2Z top view
4 an1569.1 october 5, 2010 application note 1569 ISL28233MSOPEVAL2Z schematic diagram node out in- in+ n o d e out in+ in- dnp r7 5 j16 j15 1 5 r22 j21 r31 r24 dnp 2 open 1 r25 100 dnp 1 2 j18 1 2 r23 0 r20 dnp 0 msop8 dnp dnp dnp dnp 100 dnp 0 dnp dnp 100 open 1m dnp dnp dnp 0.01 f 1f 0.01 f 100k 100k 0 100 open 0 open dnp open open 0 dnp dnp dnp dnp dnp 1f r11 12 r13 1 2 r10 12 r12 12 r15 2 r18 12 r3 12 r14 1 2 r28 1 2 r2 12 r17 1 2 r6 1 2 12 2 r29 1 2 r1 12 c9 1 2 c8 1 2 c6 1 2 c7 1 2 r27 12 r26 12 j8 1 j6 1 2 3 j1 3 1 j1 2 1 j1 4 1 j11 1 3 j4 1 2 3 4 5 j3 1 2 3 4 5 j1 1 2 3 4 5 j2 1 2 3 4 5 1 2 3 4 1 2 3 4 5 c5 c3 c4 c2 1 2 r4 12 r5 12 12 r8 12 c10 1 2 1 2 r21 1 2 r19 1 21 2 c1 1 2 d1 1 2 3 r30 1 2 r35 12 r34 2 r32 12 r36 1 j17 12 j19 12 j20 1 12 j22 1 2 j24 12 2 j23 1 2 r16 1 2 1 2 u1 1 2 3 4 6 7 8 vref vref 1 3 4 8 6 7 5 generic 2 1m in-a in+a in-b in+b out a out b v+ v- close to dut pack
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